The present invention relates to semiconductor integrated circuits containing memory arrays, and in preferred embodiments the invention particularly relates to monolithic three-dimensional memory arrays having series-connected memory cells.
Recent developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication.”
A variety of other memory cells technologies and arrangements are also known. For example, NAND flash and NROM flash EEPROM memory arrays are known to achieve relatively small memory cells. Other small flash EEPROM cells are known which use hot electron programming, such as NROM and floating gate NOR flash memory arrays.
An extremely dense memory array may be achieved using a NAND-style arrangement, which includes series-connected NAND strings of memory cell devices. Each NAND string of memory cells typically includes a first block select device which couples one end of the NAND string to a global line, a plurality of series-connected memory cells, and a second block select device which couples the other end of the NAND string to a bias node associated with the string. A memory array may include a number of memory blocks, with each block including a plurality of NAND strings which share the same word lines. Two block select signals for the block are typically routed to each NAND string of the block.
A basic NAND string is a very efficient structure, capable of achieving a 4F2 layout for the incremental transistor memory cell. Density is also improved because the block select lines may be routed in continuous polysilicon stripes across the array block, just like the word lines, without any provision being otherwise required for contacting a block select signal line to some but not all of the block select transistors formed in the NAND strings.
For many NAND string memory arrays (i.e., those employing series-connected memory cells), tradeoffs exist when choosing the various bias voltages applied to selected and unselected memory cells during programming, and the relative timing of the application of these voltages. Conditions must be chosen to ensure adequate programming of the selected memory cells, but also to ensure that unselected memory cells within the selected NAND string are not unintentionally “disturb programmed” and further to ensure that memory cells in an unselected NAND string adjacent to the selected NAND string (i.e., sharing the same word lines) are also not unintentionally disturbed during programming. Despite progress to date, continued improvement in memory array structures and methods of their operation are desired. Moreover, improvements in such memory array structures which may be fashioned into a three-dimensional memory array are highly desired.